Estimation of average multiple-valued logic circuit size using Monte Carlo simulation technique

Abstract

This paper presents a statistical approach for fast comparison of multiple-valued logic (MVL) designs. Since there are no standard benchmark functions available for MVL, the benchmark functions for binary logic were used for performance analysis of MVL circuits. An alternative would be to test all the possible multiple-valued logic functions for different input variables. However, the testing process is a very time consuming. Monte Carlo simulation (MCS) has been used in the past to explore systems involving large range of parameters. By using MCS, it is found that 150 random functions are sufficient to obtain an average circuit size of all possible 2-input, 4-valued logic functions.