Low jitter hybrid Phase Locked Loop

Abstract

In this paper, we present Low jitter hybrid Phase Locked Loop (PLL). PLL are widely used in digital communication receivers because they generate a necessary clock signal, the PLLs used in communication receivers require to generate a low-jitter clock with fast frequency and phase lock. Our hybrid PLL (HPLL) architecture consists of a LC-PLL followed by a Ring-PLL. The HPLL achieves improved jitter performance with a wide frequency range. The Ring PLL noise performance is improved using an LCPLL as a reference clock generator.