Clamped inductive turn-off failure in high-voltage NPT-IGBTs under overloading conditions

Abstract

The clamped inductive turn-off failure of NPT-IGBTs is investigated under overloading events. First, their signatures are determined. Second, physical TCAD simulations are carried out considering, for the first time, the current mismatch among the cells from the chip core, gate runner and edge termination areas. As a result, a secondary breakdown at the IGBT peripheral cells at the edge of the gate runner has been indentified to be responsible of the failure. Besides, a strategy to enhance the device robustness is proposed.