Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

Abstract

An energy-efficient high bandwidth array design using 0.0300-μm2 high performance SRAM bitcell on Intel 4 CMOS technology is presented. By employing a unique combination of design techniques, the proposed 6T SRAM array design demonstrates >80% access energy improvement over a conventional 4-way interleaved 6T SRAM array design and 30% macro density improvement compared to a hierarchical 8T SRAM design for high bandwidth memory applications.