16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Abstract

In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.