Validation of ASIP Architecture Description

Abstract

Validation is one of the most complex and expensive tasks in current Application Specific Instruction Set Processors (ASIP) design process. Many existing approaches employ a multiple-level approach to efficiently design and verify ASIP design. This paper presents a novel extended timed Petri net model called HDPN-Hardware Design based-on Petri Net to model systems at multiple levels, and introduces a verification scheme based on HDPN to satisfy the requirement of Design Space Exploration (DSE). This paper focuses on formal modeling and verification ASIP architecture. And a DLX pipelined processor is presented to demonstrate the validity and usage of this method.