Data filter cache with word selection cache for low power embedded processor

Abstract

Filter cache was proposed to reduce power consumption. The proposers inserted a small and fast cache, which is called Filter Cache, between core and L1 cache. Filter cache reduced the number of accesses to L1 cache and a significant power savings is achieved. However, because the performance loss is so severe, many researchers should adopt some components which alleviate execution delay. In this paper, we revisit the original filter cache system and identify that employing filter cache does not degrade the system performance in the modern computer system. In base of the analysis, we propose Data Filter Cache system with Word Selection Cache(DWSC) as a new solution. Because tag matching of the L1 cache occurs simultaneously with access to the filter cache, the DWSC does not suffer performance loss. The result shows that our proposal achieves the 75.9% energy savings with respect to the baseline system.