S. P. Raajhen, S. Janardhana, J. Jaya, K. J. Sabareesaan
{"title":"Design and implementation of digital RF transmitter for bluetooth applications","authors":"S. P. Raajhen, S. Janardhana, J. Jaya, K. J. Sabareesaan","doi":"10.1109/ICCTET.2013.6675952","DOIUrl":null,"url":null,"abstract":"A novel fully digital architecture for a multi gigahertz RF transmitter that meets blue tooth specifications is presented in this paper. The transmitter architecture uses All Digital Phase-locked loop. (ADPLL) in contrast to charge-pump PLLs used in analog transmitters. The ADPLL has several advantages when compared to traditional Charge-pump PLLs. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase /frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator (DCO) and a time-to-digital converter, respectively. All digital blocks are synthesized using VHDL code. The RF transmitter so created can be used for any short-range wireless applications and it can also be integrated with DSP systems as a System-on-chip (SoC).","PeriodicalId":242568,"journal":{"name":"2013 International Conference on Current Trends in Engineering and Technology (ICCTET)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Conference on Current Trends in Engineering and Technology (ICCTET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCTET.2013.6675952","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel fully digital architecture for a multi gigahertz RF transmitter that meets blue tooth specifications is presented in this paper. The transmitter architecture uses All Digital Phase-locked loop. (ADPLL) in contrast to charge-pump PLLs used in analog transmitters. The ADPLL has several advantages when compared to traditional Charge-pump PLLs. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase /frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator (DCO) and a time-to-digital converter, respectively. All digital blocks are synthesized using VHDL code. The RF transmitter so created can be used for any short-range wireless applications and it can also be integrated with DSP systems as a System-on-chip (SoC).