A three level cache structure

Abstract

Hierarchy of cache levels plays a major role for a faster memory access compared to direct main memory access for information recently used by a processor. In this paper, we propose a three level cache structure with additional decoder for much faster accesses. The three level caches maintains data redundancy and decoder helps to enable part of cache memory in each level rather than complete cache memory in each level. A piece of information from the address referencing the locations is used for enabling each way in corresponding levels. Thus the access takes less time rather than accessing the whole memory in each level. The decoder helps in enabling the way depending on few bits considered from the address to enable the desired way. A three level cache structure with L1 (2 way, 128 Kb), L2 (4 way, 128 kb) and L3 (8 way, 128 kb) has been simulated in Xilinx 9.1 ISE. The technology of decoder in each cache level improves the efficiency.