A 2.4GHz sub-1 dB CMOS low noise amplifier with on-chip interstage inductor and parallel intrinsic capacitor

Abstract

This paper presents the design of low noise amplifier with on-chip inductors integrated in a TSMC 0.18 /spl mu/m CMOS process for 2.4 GHz wireless applications. An additional capacitance in parallel with the gate capacitance of the amplifying transistor is used to optimize the noise performance with low power dissipation. An interstage inductor between the common source stage and the common gate stage is used to increase power gain. It requires only a 1.2 V supply. At 2.4 GHz and P/sub DC/ = 2.4 mW, this LNA features: noise figure = 0.76 dB with input return loss = -22.4 dB and power gain = 12.9 dB. This LNA presents the best-simulated noise figure and power dissipation performance reported for 2.4 GHz CMOS LNA.