Off-phase crosstalk behaviour and design considerations for high-speed memory buses

Abstract

The interconnect margins shrink rapidly at higher speed due to reduced bit width and increased noise level. Crosstalk impact remains the biggest concern for the single-ended memory busses such as DDR3 and GDDR5 interconnect. The phase relationship of the xtalk coupling plays an important role on interconnect performance. This paper outlines several types of off-phase crosstalk and their impact to system margin. It also provides the methodology to analyse their effects and design considerations to mitigate their impact.