Prospect of Analyzing Integrated Circuits Based on Dataset with Synthesis Results

Abstract

When designing blocks for integrated circuits, it is crucial to understand whether the module in question meets set constraints. Area and timing are important parameters which are being obtained after synthesizing the circuit with specialized tools. However, this process can be too time consuming. In this paper we present an overview of methods, which can be used to determine area and timing with a prepared dataset. Bilinear interpolation, approximation and deep neural networks are being used for this task. The results show that though the first two methods can be used in special cases, the machine learning approach is more flexible and can be effectively implemented for integrated circuit analysis.