Area-efficient Power-rail ESD Clamp Circuit with False-trigger Immunity in 28nm CMOS Process

Abstract

In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid triggering mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed area-efficient power clamp circuit is capable of achieving μs-level transient response time with an RC time constant of 10 ns and avoiding triggering under fast power-on conditions. In addition, the circuit also has low standby leakage current under normal power-on conditions.