Design and Optimization of 6nm Finfet Tunneling Effect under Overlap and Underlap Condition

Abstract

FinFET is a type of multi-gate Metal Oxide Semiconductor Field Effect Transistor where gate covers around the slim tri-gate FinFET [1]. Since the channels are completely surrounded by the gate, the overall inversion layer is larger, which results more drain current. It can be optimized with multiple fins. This structure also characterize very little leakage current flow through the body when the transistor is in OFF state and therefore results in optimized performance and low static power.