Fast low-energy VLSI binary addition

Abstract

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition as carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt/sub fa/, to Wt/sub mux/ where t/sub fa/ and t/sub mux/ respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using lookahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that fastest binary addition can be performed using (Wlog/sub 2/+W+1) multiplexers in time (log/sub 2/W+2)t/sub mux/. If the specified adder latency is greater than (log/sub 2/W+2)t/sub mux/, then a family of converters using fewest multiplexers can be designed based on carry-select approach. Finally a class of hybrid adders are designed by using a carry-select configuration and by substituting tree-based blocks in place of some carry-select blocks. It is shown that this approach can lead to adder designs which consume the least energy.