Bridging faults modeling and detection in CMOS combinational gates

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224371

G. Buonanno, D. Sciuto

引用次数: 1

Abstract

A method based on the detectability of bridging faults through test sets developed to locate other types of faults is presented. In particular it will be shown how bridging faults can be detected in CMOS combinational circuits using a test procedure that detects transistor stuck-at faults in a new design for testability for fully CMOS logic. The detection of more than 95% of the possible bridging faults (single and multiple) is achieved.<>

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CMOS组合门的桥接故障建模与检测

提出了一种基于桥接故障可检测性的测试集故障定位方法。特别是，它将展示如何在CMOS组合电路中使用测试程序检测桥接故障，该测试程序检测晶体管卡在故障的新设计，以实现完全CMOS逻辑的可测试性。实现了95%以上的可能桥接故障(单个和多个)的检测

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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