Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuits

Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95 Pub Date : 1995-02-21 DOI:10.1109/PEDS.1995.404890

M.T. Zhang, M. Jovanovic, F. Lee

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引用次数: 196

Abstract

By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. A variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These on-board power supplies will be derived from the existing voltages available in the system (usually 5 V or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics.<>

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用于下一代数据处理电路的低压板载DC/DC模块的设计考虑

通过降低电源电压，可以实现更高的速度、更低的功耗和更高的数据处理集成电路的集成密度。可提供从3.3 V工作的各种ic。下一代ic有望在更低的电压下工作，即在1-3 V范围内，以进一步提高其速度功率性能。同时，在瞬态期间，这些新一代数据ic将呈现非常动态的负载，具有高电流转换率。因此，它们将需要负载点电源，以尽量减少互连寄生的影响。这些板载电源将来自系统中现有的可用电压(通常为5v或12v)，并且需要具有高功率密度，高效率和良好的瞬态性能。本文介绍了这些板载电源的设计注意事项，并讨论了各种电路和系统寄生对其性能的限制。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95

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