Codimensional Optimization of Differential Via Padstacks

Abstract

In printed circuit boards, vias are needed when signals make layer transitions. Typically, via transitions are defined through padstacks. These padstacks provide geometrical manufacturing characteristics of the transitions such as via drill size, pad size, antipad size and thermal tolerance. Differential via design consists of padstack definition and relative positioning to other padstacks such as signal and reference as well as entry and exit trace parameters. At high speeds, vias cause reflections if they are not well designed. When stack-ups have a lot of signal layers, optimizing via padstack for each signal transition is going to be cumbersome. Using a padstack optimized for one signal transition on other transitions may degrade signal performance. In this work, a simultaneous codimensional optimization to differential via padstack designs is proposed to optimize a single padstack definition so that it can handle multiple entry/exit layer transitions.