Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu
{"title":"The Secret Processor Will Go to the Ball: Benchmark Insider-Proof Encrypted Computing","authors":"Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu","doi":"10.1109/EuroSPW.2018.00027","DOIUrl":null,"url":null,"abstract":"‘Encrypted computing’ is an approach to preventing insider attacks by the privileged operator against the unprivileged user on a computing system. It requires a processor that works natively on encrypted data in user mode, and the security barrier that protects the user is hardware-based encryption, not access. We report on progress and practical experience with our superscalar RISC class prototype processor for encrypted computing and supporting software infrastructure. This paper aims to alert the secure hardware community that encrypted computing is possibly practical, as well as theoretically plausible. It has been shown formally impossible for operator mode to read (or write to order) the plaintext form of data originating from or being operated on in the user mode of this class of processor, given that the encryption is independently secure. Now we report standard Dhrystone benchmarks for the prototype, showing performance with AES-128 like a 433MHz classic Pentium (1 GHz base clock), thousands of times faster than other approaches.","PeriodicalId":326280,"journal":{"name":"2018 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EuroSPW.2018.00027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
‘Encrypted computing’ is an approach to preventing insider attacks by the privileged operator against the unprivileged user on a computing system. It requires a processor that works natively on encrypted data in user mode, and the security barrier that protects the user is hardware-based encryption, not access. We report on progress and practical experience with our superscalar RISC class prototype processor for encrypted computing and supporting software infrastructure. This paper aims to alert the secure hardware community that encrypted computing is possibly practical, as well as theoretically plausible. It has been shown formally impossible for operator mode to read (or write to order) the plaintext form of data originating from or being operated on in the user mode of this class of processor, given that the encryption is independently secure. Now we report standard Dhrystone benchmarks for the prototype, showing performance with AES-128 like a 433MHz classic Pentium (1 GHz base clock), thousands of times faster than other approaches.