Determining "OFF" Time Duration of FPGA basec GPS Tracking System*

Abstract

Abstract—In the world of configurable computing, field programmable gate arrays (FPGAs) plays a prominent role. FPGAs give the ability to implement custom hardware functions with the use of prebuilt logic blocks and programmable routing of resources. It also provides the best parts of both ASICs and processor based systems. With the tremendous increase in application and use of FPGA, the need for security to the data produced is immensely high. One such key security factor the current FPGAs in the industry fall short of is determining the OFF time duration. This would be a major threat to the data produced by FPGAs in time sensitive applications. In time sensitive applications, if the off time duration of FPGA is not ensured then, the data produced by the FPGA would be rather obsolete or not very useful without some pre-processing. When larger designs are implemented on FPGAs, they are likely to have multiple clocks running on different paths. Due to FPGAs infinite length clocks, you can create as many clocks as you want with the help of PLL or DCMs. Thus to determine its OFF time is difficult and challenging. To tackle this problem, this paper deals with one such solution of determining OFF duration of FPGA with the help of Arduino. In this paper, one such application that is GPS tracking system is implemented. In order to improve the reliability of that system, the OFF time measurement is measured and verified with real clock to check intentionally making the system power off.