A 43Gb/s 2:1 selector IC in 90nm CMOS technology

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332682

T. Yamamoto, M. Horinaka, D. Yamazaki, H. Nomura, K. Hashimoto, H. Onodera

引用次数: 11

Abstract

The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.

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采用90nm CMOS技术的43Gb/s 2:1选择IC

2:1选择器IC由3级输入缓冲器、1级2:1选择器和2级输出缓冲器组成。该电路采用多重感应峰值和选择器结构抑制干扰，数据速率为43Gb/s，采用90nm CMOS技术和48nm晶体管实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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