Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching

Abstract

This paper proposes a reconfigurable hardware architecture of modified KD-tree machine-learning classifier. As compared to current literature, this hardware is the first KD-tree-like hardware implementation. As compared with original KD-tree algorithm, our design can deliver a very low latency in hardware because we do not need the data traversal steps along the binary tree. Meanwhile, this scalable hardware can be easily constructed if supporting a greater number of data instances to be classified. In the hardware implementation with TSMC 40-nm CMOS technology, our synthesizable hardware achieves a maximum frequency of 401.6 MHz, only occupying an area of 0.562 mm2.