B. Obulesu, K. V. Raju, P. S. Sumanth, A. Vamsi, C. Kiran
{"title":"Design and Implementation of Crosstalk Noise Avoidance by using Advanced Test Adapted Shielding for high speed vlsi circuits","authors":"B. Obulesu, K. V. Raju, P. S. Sumanth, A. Vamsi, C. Kiran","doi":"10.1109/ESCI56872.2023.10100085","DOIUrl":null,"url":null,"abstract":"The Crosstalk noise is existing in VLSI circuits because of the electromagnetic coupling in between the wires unfriendly, it affects the VLSI circuits accurate performance. This makes interconnect testing a vital issue in responsibility analysis that causes additional space and hardware operating overhead[2]. In this project, we have a tendency to gift a completely unique methodology that we have a tendency to talk over with advanced Test Adaptive Shielding (TAS), so as to boost testing challenges and in addition to optimize crosstalk noise. Boosting of circuit performance is done by test structure at Test adapted shielding which includes the insertion of modified shield lines. The Hardware which is being developed for test data is sensible to ignore the aggregation faced by victim lines due to crosstalk noise. The main methodology of TAS method is to reduce he over use of power, complex nature, fault detection. The projected technique will implement in ASIC, VERILOG HDL.","PeriodicalId":441215,"journal":{"name":"2023 International Conference on Emerging Smart Computing and Informatics (ESCI)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 International Conference on Emerging Smart Computing and Informatics (ESCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESCI56872.2023.10100085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The Crosstalk noise is existing in VLSI circuits because of the electromagnetic coupling in between the wires unfriendly, it affects the VLSI circuits accurate performance. This makes interconnect testing a vital issue in responsibility analysis that causes additional space and hardware operating overhead[2]. In this project, we have a tendency to gift a completely unique methodology that we have a tendency to talk over with advanced Test Adaptive Shielding (TAS), so as to boost testing challenges and in addition to optimize crosstalk noise. Boosting of circuit performance is done by test structure at Test adapted shielding which includes the insertion of modified shield lines. The Hardware which is being developed for test data is sensible to ignore the aggregation faced by victim lines due to crosstalk noise. The main methodology of TAS method is to reduce he over use of power, complex nature, fault detection. The projected technique will implement in ASIC, VERILOG HDL.