Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs

M. Hariyama, Weisheng Chong, S. Ogata, M. Kameyama
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引用次数: 6

Abstract

Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained reconfigurable architecture called reconfigurable context memory (RCM) is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. A floating-MOS functional pass-gate, where storage and switch functions are merged, is used to construct the RCM area-efficiently.
基于非易失性功能栅极的多上下文fpga开关块结构
动态可编程门阵列(DPGAs)比传统fpga实现成本更低,因为它们可以有效地及时重用有限的硬件资源。典型的DPGA体系结构之一是多上下文体系结构。多上下文fpga (mc - fpga)每个配置位有多个存储位,形成配置平面,以便在上下文之间快速切换。额外的存储平面在面积和功耗方面造成显著的开销。为了克服这种开销,基于不同上下文之间的配置位存在冗余性和规律性这一事实,提出了一种称为可重构上下文内存(RCM)的细粒度可重构架构。采用融合存储功能和开关功能的浮动mos功能通闸,有效地构建了RCM区域。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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