Synthesis of multi-variable MVL functions using hybrid mode CMOS logic

Abstract

This paper presents a new scheme for synthesizing any multi-variable MVL (Multi-Valued Logic) function. The scheme utilizes a hybrid approach, i.e. a combination of the current mode and the voltage mode CMOS circuits, to synthesize MVL functions. Due to better utilization of circuit components, it can reduce the transistor count (cost) of the synthesized circuits about one half as compared with those using the MIN-MAX gates and literals or the T-gates. Also, an extra noise margin added in the design eliminates the need of the threshold detection circuit to recover the signal in this scheme.<>