A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications

Abstract

Due to the limited energy supply of wireless sensor nodes, minimizing their power consumption has become a primary concern to increase their battery lives. These sensor nodes require clock signals to process data and to synchronize with other sensor nodes in the network. However, clock generator circuits usually consume a lot of power. This work addresses this problem by implementing a low-power all-digital phase-locked loop (ADPLL) in a 65nm CMOS process with a low operating voltage of 0.5V. Its output frequency range is 0.285 – 48MHz with a power consumption of 8.25µW at 23MHz. With the use of the frequency estimation algorithm, the ADPLL is able to achieve fast lock-in time within 5 reference clock cycles with frequency errors of less than 1.5%.