Low Power and High Performance Ring Counter Using Pulsed Latch Technique

Abstract

In this work, the performance of ring counter is improved using pulsed latch technique. In high speed and low power VLSI applications where heavy pipelining is used, there is requirement of low power edge triggered flip flops. The migration from flip flop to pulsed latch has become great success in low power VLSI application. The proposed circuit has been designed using Cadence Virtuoso in 90 nm CMOS technology. The pulse latch technique reduces the power consumption significantly in the designed circuit and overall there is an improvement in power delay product. The proposed circuit also require less number of transistors for its implementation as compared to conventional version.