Track-and-hold and comparator for a 12.5GS/s, 8bit ADC

Abstract

This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8bit, 12.5GS/s folding-interpolating analog to digital converter (ADC) with a 3GHz bandwidth. The circuits are implemented in a 0.25µm, 190GHz SiGe BiCMOS process. The THA occupies an area of 0.5mm2. It features a SNDR of 47dB or 7.5bits ENOB for a 3GHz bandwidth, a hold time of 21ps with a droop rate of 11mV/80ps and a power dissipation of 230mW from a 3.3V supply. The comparator occupies an area of 0.38mm2 and exhibits an input sensitivity of ±2mV, an input offset voltage of 1.5mV, latch and recovery times of 19 and 21ps respectively and a power dissipation of 150mW from a 3.3V supply.