{"title":"High voltage SOI MESFETs at the 45nm technology node","authors":"W. Lepkowski, S. Wilk, M. R. Ghajar, T. Thornton","doi":"10.1109/SOI.2012.6404403","DOIUrl":null,"url":null,"abstract":"Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International SOI Conference (SOI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2012.6404403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.