Modeling of memristor device & analysis of stability issues

Abstract

A robust physical model governing trap assisted inelastic tunneling mechanism for the conducting area of a memristor device with an intermediate thickness dielectric (<100nm) has been developed. This model takes into account, the contribution of both the oxygen vacancies and the defects within the oxide responsible for the significant increase of charge carriers through this non-volatile memory device. A one dimensional simulator has been designed here that shows reasonable compatibility between the practically obtained values with that of the simulated ones. Here tunneling of electrons between variable energy states of the different layer materials within the device, dominates the switching mechanism that involves a strong non-linearity of the electric field dependence.