Clustered programmable-reconfigurable processors

Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, N. Carter
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引用次数: 18

Abstract

In order to pose a successful challenge to conventional processor architectures, reconfigurable computing systems must achieve significantly better performance than conventional programmable processors by both greatly reducing the number of clock cycles required to execute a wide range of applications and achieving high clock rates when implemented in deep-submicron fabrication technologies. In this paper, we describe the architecture of Amalgam, a clustered programmable-reconfigurable processor that integrates multiple conventional processors and blocks of reconfigurable logic onto a single chip. Amalgam's distributed architecture allows implementation at high clock rates by limiting the impact of wire delay on cycle time and delivers an average of 13.7/spl times/ speedup on our benchmark applications when compared to an equivalent architecture that contains only a single programmable processor.
集群可编程可重构处理器
为了对传统处理器架构提出成功的挑战,可重构计算系统必须通过大大减少执行广泛应用所需的时钟周期数量和在深亚微米制造技术中实现高时钟速率来实现比传统可编程处理器更好的性能。在本文中,我们描述了Amalgam的体系结构,这是一种集群可编程可重构处理器,它将多个常规处理器和可重构逻辑块集成到单个芯片上。Amalgam的分布式架构通过限制线延迟对周期时间的影响,允许在高时钟速率下实现,与仅包含单个可编程处理器的等效架构相比,我们的基准应用程序平均提供13.7/spl次/加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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