Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

Abstract

In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.