Design of high-density power lateral DMOS transistors

Abstract

Significant reduction in the surface area required for high voltage lateral DMOS transistors (LDMOSTs) has been achieved. Application of a recently developed field shaping technique has resulted in transistors exhibiting breakdown voltages well in excess of the planar junction limit. Further extensions of the method predict LDMOSTs having active surface area less than or comparable to vertical MOS devices without sacrificing breakdown voltage or on-resistance.