Stress Tuning in NanoScale FinFETs at 7nm

Abstract

In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.