A 28-GHz-band Stacked FET Linear Power Amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

2019 IEEE Radio and Wireless Symposium (RWS) Pub Date : 2019-05-14 DOI:10.1109/RWS.2019.8714268

Cuilin Chen, T. Sugiura, T. Yoshimasu

引用次数: 1

Abstract

This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

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一种基于56nm SOI CMOS的28 ghz频带堆叠FET线性功率放大器IC，在P1dB和3db之间具有36.2%的PAE

提出了一种用于5G无线通信系统的高效率线性堆叠FET功率放大器(PA) IC。采用自适应偏置电路，提高了线性度和回退效率。此外，三阶跨导分量(gm3)被多级联码结构抵消。该PA IC是在56纳米SOI CMOS中设计、制造和全面评估的。在4 V电源电压下，PA IC在1 db增益压缩点(P1dB)的输出功率为20.0 dBm, PAE为38.1%。与P1dB相比，3db和6db的PAEs分别为36.2%和28.7%。得到25.0 dBm的输出IP3。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2019 IEEE Radio and Wireless Symposium (RWS)

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