Block-based SRAM architecture and thermal-aware memory mappings for three-dimensional channel decoding systems

Abstract

In this work, the 3D block-based SRAM architecture and the thermal-aware memory mappings are proposed for the 3D channel decoding systems. The 3D block-based SRAM is proposed by analyzing the memory utilization with different sizes of the memory elements. Based on this architecture, the thermal-aware memory mappings are discussed by minimizing the vertical stacking of the active MEs and avoiding the successive access of the MEs. In our experiments, the peak temperature can be reduced by 2.6°C ~ 22.2°C compared to the worst mappings.