Design and Simulation of Two Stage Sample and Hold Circuit with Low Power using Current Controlled Conveyor

Abstract

Two Stage Sample and Hold Circuit: In first stage, two-identical sample and hold circuits are connected in cascaded topology. In second stage, the output from first stage of sample and hold circuit is rectified again and the current conveyor is used as a switch which is controlled by the bias current pulses. Both the stages of sample and hold circuit are synched with each other and operate at same bias current with low power consumption. The features of proposed circuit has more accurate results with high linearity as well as more flatter output output waveform at the hold time. The proposed sample and hold circuit has been simulated using $\mathbf{0.18}\quad\mu\mathbf{m}$ complementary metal oxide (CMOS). The major interest is the simulation of an analog switch used in the circuit.