An approach for customizing on-chip interconnect architectures in SoC design

Abstract

Recent studies have shown that to improve the performance of specific System-on-Chip (SoC) application domain, the OCI (On-Chip Interconnect) architecture must be customized, at design time. These approaches are generally tailored to a specific application, providing an application-specific SoC. They deal with the selection of OCI architecture to accommodate the expected application specific data traffic pattern during early design-space exploration phase. For dynamic SoCs, in which traffic pattern of applications is not known or predictable in advance, an efficient OCI is required. In this paper, we present an approach to allow designers to customize a candidate OCI architecture in order to match large application workload. Simulations results, using 2D mesh, show that this method achieves better performance compared to the basic 2D mesh OCI architecture, while using little resource budget.