Power-optimal repeater insertion considering V/sub dd/ and V/sub th/ as design freedoms

Abstract

This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and V/sub dd/ and V/sub th/ levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider V/sub dd/ and V/sub th/ optimization. This work further presents the power saving when multiple V/sub dd/ and V/sub th/ levels are used in repeater insertion at the full-chip level. Compared to the case with single V/sub dd/ and V/sub th/ suggested by ITRS, optimized dual V/sub dd/ and dual V/sub th/ reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra V/sub dd/ or V/sub th/ levels only give marginal improvement. We also show that an optimized single V/sub th/ reduce interconnect power almost as effective as dual-V/sub th/ does, in contrast to the need of dual V/sub th/ for logic circuits.