Evaluation of Low-k Integration Integrity Using Shear Testing on Sub-30 Micron Micro-Cu Pillars

Tae-Kyu Lee, Greg Baty, O. Ahmed, P. Su, Bernard Glasauer
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Abstract

Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.
基于剪切试验的亚30微米微铜柱低k集成完整性评价
对于使用先进硅节点的器件来说,低k介电薄膜的机械完整性仍然是一个质量和可靠性方面的挑战。在晶圆厂,虽然在控制和监控单个加工步骤方面付出了巨大的努力,但通常无法有效地监控特定设备的整体机械质量。界面分层等缺陷可能仅在系统组装过程中或现场操作中出现,对生产和产品质量造成重大干扰和影响。随着硅尺寸和封装尺寸的不断增长,芯片封装相互作用变得更加重要,因此低k相关故障的风险也随之增加。特别是对于3D和2.5D器件,芯片堆叠的复杂性使得对介电质量进行定量评估对于良率和持续可靠性管理都很重要。在2.5D和3D器件上采用微铜柱为直接测量集成质量提供了机会。如果可以对单个微铜柱进行剪切测试,则可以对此类测试的响应进行分析和量化,作为集成质量的直接测量。此外,这样的测试可以在感兴趣的特定设备和模具上的特定位置进行,这使得有可能使用这种技术作为产品质量控制方法。本文将报道亚30微米微铜柱的剪切试验结果。将报告来自多个晶圆、晶片和凸点位置的数据。分析了载荷-距离曲线和最大断裂载荷等响应。此外,还建立了多级有限元模型来模拟剪切试验。应力集中的位置将被识别,并与剪切试验中的断裂界面进行比较。还将研究介电层特性变化的响应,从而深入了解在实际share测试中观察到的剪切强度变化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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