Florian Voineau, B. Martineau, Mathilde Sié, A. Ghiotto, E. Kerhervé
{"title":"A High-Speed Millimeter-Wave QPSK Transmitter in 28nm CMOS FD-SOI for Polymer Microwave Fibers Applications","authors":"Florian Voineau, B. Martineau, Mathilde Sié, A. Ghiotto, E. Kerhervé","doi":"10.23919/EuMIC.2019.8909564","DOIUrl":null,"url":null,"abstract":"Benefiting from considerable progress in the design of low-power, low cost and high-speed millimeter-wave circuits, Polymer Microwave Fibers (PMF) are gaining interest in the context of serial links. In this work, an innovative dual-band Quadrature Phase Shift Keying (QPSK) architecture, which is based on integrated wideband and low loss differential hybrid couplers, is proposed to increase data rate capability while still preserving low power and moderate range potentials. A circuit demonstrator in 28 nm CMOS FD-SOI is presented to validate the concepts. It achieves fifth harmonic locking on a wide continuous locking range and realizes 9 Gb/s data rate in the E-band.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EuMIC.2019.8909564","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Benefiting from considerable progress in the design of low-power, low cost and high-speed millimeter-wave circuits, Polymer Microwave Fibers (PMF) are gaining interest in the context of serial links. In this work, an innovative dual-band Quadrature Phase Shift Keying (QPSK) architecture, which is based on integrated wideband and low loss differential hybrid couplers, is proposed to increase data rate capability while still preserving low power and moderate range potentials. A circuit demonstrator in 28 nm CMOS FD-SOI is presented to validate the concepts. It achieves fifth harmonic locking on a wide continuous locking range and realizes 9 Gb/s data rate in the E-band.