FPGA Implementation of FSM based Viterbi Decoder

Abstract

Mobile communications has evolved from 1G to 5G with the current number of users for increased from 5 percent to 95 percent and 4G-LTE are 95 percent all over the world according to ITU. In 2G communication system, only voice data was transmitted at 64 kbps.4G-LTE communication is Internet Protocol-based which increased data rates to a higher level of 200 Mbps along with voice, video, and Internet are used. To meet the user requirements different coding schemes are implemented in different mobile technologies for 2G/4G-convolutional codes, 4G-Turbo codes to accommodate the data rates. Convolution codes are widely used in 4G communication systems to encode the information bits to accommodate the channel capacity. Convolutional codes are a class of cyclic codes that are implemented in communication systems to transmit a large amount of data wirelessly. The 4G technology uses a Viterbi algorithm to decode the information bits encoded by convolutional encoding but 4G uses turbo-codes, which offers better performance over convolutional codes. The convolutional encoding is implemented based on the polynomial equation and decoding is performed by the Viterbi algorithm. The Viterbi algorithm uses maximum likelihood estimation to decode the information bits. This paper presents FPGA implementation of Traceback method, FSM based Viterbi with constrained lengths of $\mathrm{K}=3,\mathrm{K}=5$ of coding rate 1/2 on Vivado-HLS design, and results were observed.