Yang Guo, Shaolin Xie, Zijun Liu, Lei Yang, Donglin Wang
{"title":"Parallel Polar Encoding in 5G Communication","authors":"Yang Guo, Shaolin Xie, Zijun Liu, Lei Yang, Donglin Wang","doi":"10.1109/ISCC.2018.8538743","DOIUrl":null,"url":null,"abstract":"Because of its theoretical capacity-achieving property, polar code has become the coding scheme of the control channel in the 5G communication standard. Although its encoding complexity is low, the data dependency in polar code makes it difficult to parallelize. This paper proposes a parallel polar encoding method for 5G communication and evaluates its performance with extended digital signal processor (DSP) instructions. Compared with the existing field-programmable gate array (FPGA) implementation, the performance improved by $300 \\times$ with negligible area and power overhead. The extended instructions are based on our in-house DSP architecture, but the parallel scheme is applicable to other single instruction multiple data (SIMD) architectures.","PeriodicalId":233592,"journal":{"name":"2018 IEEE Symposium on Computers and Communications (ISCC)","volume":"8 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on Computers and Communications (ISCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCC.2018.8538743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Because of its theoretical capacity-achieving property, polar code has become the coding scheme of the control channel in the 5G communication standard. Although its encoding complexity is low, the data dependency in polar code makes it difficult to parallelize. This paper proposes a parallel polar encoding method for 5G communication and evaluates its performance with extended digital signal processor (DSP) instructions. Compared with the existing field-programmable gate array (FPGA) implementation, the performance improved by $300 \times$ with negligible area and power overhead. The extended instructions are based on our in-house DSP architecture, but the parallel scheme is applicable to other single instruction multiple data (SIMD) architectures.