{"title":"A robust chip capacitor for video band width in RF power amplifiers","authors":"A. A. Aziz, F. Danaher, A. Hashim","doi":"10.1109/EPTC.2014.7028263","DOIUrl":null,"url":null,"abstract":"Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"181 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2014.7028263","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.