An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture

Abstract

With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multiprotocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm2 in a UMC 0.18 mum CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area.