A reduced-swing data transmission scheme for resistive bus lines in VLSIs

Abstract

An optimal design method of on-chip communication circuits is presented, where a reducing signal swing scheme is employed using termination resistors and sense amplifiers. Although this method treats distributed capacitance and resistance in bus lines as lumped elements, it is demonstrated that the error introduced is small. With an optimum circuit designed by this method, a low power design compared with the conventional buffer-chained circuit is realized without changing system level design in the ASIC as well.<>