L. Kang, Jay Kim, JK Lee, WS Shin, N. Kim, SY Park
{"title":"nSiP(System in Package) Platform for various module packaging applications","authors":"L. Kang, Jay Kim, JK Lee, WS Shin, N. Kim, SY Park","doi":"10.1109/ECTC32696.2021.00020","DOIUrl":null,"url":null,"abstract":"nSiP(nepes System in Package) platform technology has been developed and verified as a module concept SiP package which can contain various dies and multi passives by using WLP and fan-out related technologies for various applications. nSiP platform technology has been proven to be enabling less stack up of metal routing layers due to fine 5/5 um line and spaces capabilities and improving the electrical performance. nSiP platform technology is a basic structure based on the fabricated redistribution layer for double side substrate technology, high density and double side mount technology, embedded trace substrate even without conventional PCB substrate technology. The process of nSiP module consists of Pattern process, Surface mounting (SMT) and Encapsulation (& B/E). Pattern process is a main process to fabricate redistribution layer on carrier and all process has been developed and proven with reliability tests. The fabricated redistribution layer has been developed with low Dk/Df dielectric materials. In order to validate, EVT(Engineering Validation Test) vehicle has been designed. nSiP module size which includes Components with 3-die and 65-passvie is $10\\times 10\\ \\ \\text{mm}$ with thickness 1 mm. The fabricated redistribution layer consists of 4-metal and 4-passivation layers in daisy chain format for reliability test nSiP platform technology can reduce overall module size down to 31% compared to conventional system in package technology. EMI shielding structure has been developed. Panel Level Package technology will add further benefit of cost competitiveness. Since each customer has their own SiP requirement, nSiP platform technology can be a solution as SiP module for any applications and any structures which can include any functions, like 3D PoP, double side SiP, 5G mmWave package solution and so on.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00020","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
nSiP(nepes System in Package) platform technology has been developed and verified as a module concept SiP package which can contain various dies and multi passives by using WLP and fan-out related technologies for various applications. nSiP platform technology has been proven to be enabling less stack up of metal routing layers due to fine 5/5 um line and spaces capabilities and improving the electrical performance. nSiP platform technology is a basic structure based on the fabricated redistribution layer for double side substrate technology, high density and double side mount technology, embedded trace substrate even without conventional PCB substrate technology. The process of nSiP module consists of Pattern process, Surface mounting (SMT) and Encapsulation (& B/E). Pattern process is a main process to fabricate redistribution layer on carrier and all process has been developed and proven with reliability tests. The fabricated redistribution layer has been developed with low Dk/Df dielectric materials. In order to validate, EVT(Engineering Validation Test) vehicle has been designed. nSiP module size which includes Components with 3-die and 65-passvie is $10\times 10\ \ \text{mm}$ with thickness 1 mm. The fabricated redistribution layer consists of 4-metal and 4-passivation layers in daisy chain format for reliability test nSiP platform technology can reduce overall module size down to 31% compared to conventional system in package technology. EMI shielding structure has been developed. Panel Level Package technology will add further benefit of cost competitiveness. Since each customer has their own SiP requirement, nSiP platform technology can be a solution as SiP module for any applications and any structures which can include any functions, like 3D PoP, double side SiP, 5G mmWave package solution and so on.