Cascaded tunable distributed amplifiers for serial optical links: Some design rules

Abstract

In the framework of circuits for 5G, this paper presents an innovative power efficient method to design cascaded distributed amplifiers. Validation is achieved with a 55-nm CMOS technology by ST -Microelectronics developed for the mm-wave range. Several rules are specified for analysis and design of an optimum structure, making the part between the number of trans conductances to be distributed and the number of distributed stages to be cascaded. Attention is also paid to the trade-off between power consumption and tunability. The Cadence Virtuoso tool is used to simulate the design which shows a targeted gain of 20 dB±0.8 dB over a bandwidth of 120 GHz with a power consumption of 174mW and an estimated area of 0.3 mm2.