An LDO-based supply referencing 10b 32MS/s pipelined ADC

Chang-Kyo Lee, Ji-Wook Kwon, Sang-Hyun Cho, S. Ryu
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Abstract

A reference driver-free pipelined ADC with a low drop-out (LDO) regulator for power supply is proposed for SoC applications. An LDO-based regulated voltage provides not only power supply for digital and analog circuits but also works as a reference voltage for the ADC. Conventional residue function from a 2.5b/stage design can use its max input as much as 93% of the internal supply voltage. A prototype 10-bit 32MS/s ADC has been designed for a 0.18µm CMOS technology. Under a regulated 1.5V internal supply from an external 1.8V, the design shows 65.1dB SFDR with 7.06mA (including LDO) current consumption.
基于ldo的电源参考10b 32MS/s流水线ADC
提出了一种用于SoC应用的参考无驱动器流水线ADC,具有低差(LDO)稳压器。基于ldo的稳压电压不仅可以为数字和模拟电路提供电源,还可以作为ADC的参考电压。2.5b/级设计的常规剩余函数可以使用其最大输入高达内部电源电压的93%。基于0.18µm CMOS技术设计了一个10位32MS/s原型ADC。在外部1.8V稳压1.5V内部电源下,该设计显示出65.1dB SFDR和7.06mA(包括LDO)电流消耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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