A 6T-SRAM-Based Computing-In-Memory Architecture using 22nm FD-SOI Device

Abstract

A computing in-memory architecture based on 22nm Fully Depleted Silicon On Insulator (FD-SOI) device is presented. By using FD-SOI devices, logic operations such as “and” “nor” or “ x “ Access Memory (SRAM) through the effect of body biasing in the $22\mathrm{~nm}$ FD-SOI technology. The proposed architecture contains six modules: the SRAM-based Computing InMemory module, the Data Buffer module, the Pulse Generation module, the pre-charge module, AdditionActivation-Binarization module and the System Controller module. Complex ADC and DAC circuits are not involved in this design. Thereby, by using the FD-SOI devices, the convolution or dot product operations can be realized, which are always used in artificial intelligence (AI) algorithms in a very efficient way. A Binary Multi-Layer Perception (BMLP) is mapped to examine the design. Simulations shows that our design achieves 94% accuracy in the MNIST digit recognition task. And the energy efficiency is 73.03 TOPS/W, which is far beyond traditional AI accelerators and provides an efficient path for massive computing in-memory operation.